From ymacdonald@cam.ac.uk Wed May 17 23:50:02 1995 Path: ashpoly!cascade!transat!ukc!fennimore!cam!ymacdonald From: ymacdonald@cam.ac.uk (Yuki MacDonald) Newsgroups: comp.sys.m68k Subject: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May17.235002.7927@cam.ac.uk> Date: Wed, 17 May 1995 23:50:02 GMT Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: NewsWatcher 2.0b24 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Yuki MacDonald Tape trading list upon request. SASE required for international mail. From mpopov@inria.fr Fri May 19 02:49:02 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!inria!mpopov From: mpopov@inria.fr (Morag Popov) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May19.024902.9783@inria.fr> Date: Fri, 19 May 1995 02:49:02 GMT References: <1995May17.235002.7927@cam.ac.uk> Organization: INRIA Rocquencourt NNTP-Posting-Host: inria.fr X-Newsreader: NewsWatcher 2.0b24 Lines: 12 In article <1995May17.235002.7927@cam.ac.uk>, ymacdonald@cam.ac.uk (Yuki MacDonald) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Netscape 1.1 crashes when loading large preformatted text. Stick to rn or tin! -- Morag Popov | mpopov@inria.fr PGP Key fingerprint: 42C5 FE5E 7E15 683E "Keep the channels open." From alee@clari.net Sat May 20 03:50:02 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!clari!alee From: alee@clari.net (Anton Lee) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May20.035002.7068@clari.net> Date: Sat, 20 May 1995 03:50:02 GMT References: <1995May17.235002.7927@cam.ac.uk> Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: NewsWatcher 2.0b24 Lines: 12 In article <1995May17.235002.7927@cam.ac.uk>, ymacdonald@cam.ac.uk (Yuki MacDonald) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Top-posters will be placed in my ~/.killfile without notice. -- Anton Lee *PLONK* filter active for trolls. Sun SparcStation 20 - NetBSD 1.0 From mkang@u-tokyo.ac.jp Sun May 21 12:40:02 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!u-tokyo!mkang From: mkang@u-tokyo.ac.jp (Mikhail Kang) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May21.124002.5079@u-tokyo.ac.jp> Date: Sun, 21 May 1995 12:40:02 GMT References: <1995May17.235002.7927@cam.ac.uk> Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1995May17.235002.7927@cam.ac.uk>, ymacdonald@cam.ac.uk (Yuki MacDonald) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. -- Mikhail Kang | mkang@u-tokyo.ac.jp PGP Key fingerprint: 84FF 97FF 9477 460D "Keep the channels open." From teriksson@kth.se Tue May 23 00:54:02 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!kth!teriksson From: teriksson@kth.se (Thiago Eriksson) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May23.005402.1264@kth.se> Date: Tue, 23 May 1995 00:54:02 GMT References: <1995May17.235002.7927@cam.ac.uk> <1995May20.035002.7068@clari.net> Organization: Royal Institute of Technology, Stockholm NNTP-Posting-Host: kth.se X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1995May20.035002.7068@clari.net>, alee@clari.net (Anton Lee) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. > Top-posters will be placed in my ~/.killfile without notice. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Thiago Eriksson Opinions expressed are solely my own and not those of Royal Institute of Technology, Stockholm. ------------------------------------------------------------