From mfischer@tum.de Sat Mar 26 09:57:43 1994 Path: ashpoly!cascade!transat!sunet!nordrelay!tum!mfischer From: mfischer@tum.de (Mathieu Fischer) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Mar26.095743.6554@tum.de> Date: Sat, 26 Mar 1994 09:57:43 GMT Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: Netscape 1.1N Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- === Mathieu Fischer === Dept of Electrical Engineering, Technische Universität München "A soul is not exclusive to biology." From rsokolov@cern.ch Sun Mar 27 14:48:43 1994 Path: ashpoly!bigsur!pacrim!krgate!eunha!cern!rsokolov From: rsokolov@cern.ch (Raj Sokolov) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Mar27.144843.5488@cern.ch> Date: Sun, 27 Mar 1994 14:48:43 GMT References: <1994Mar26.095743.6554@tum.de> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1994Mar26.095743.6554@tum.de>, mfischer@tum.de (Mathieu Fischer) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Raj Sokolov Zyxel U-1496E @ 33,600 bps "The hatch is open. Is anyone listening?" From bmoreno@uu.net Sun Mar 27 18:16:43 1994 Path: ashpoly!cascade!transat!ukc!fennimore!uu!bmoreno From: bmoreno@uu.net (Bruno Moreno) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Mar27.181643.2038@uu.net> Date: Sun, 27 Mar 1994 18:16:43 GMT References: <1994Mar26.095743.6554@tum.de> Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1994Mar26.095743.6554@tum.de>, mfischer@tum.de (Mathieu Fischer) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? -- === Bruno Moreno === Dept of Electrical Engineering, UUNET Technologies, Falls Church VA "Do not worship the copy."