From fchoi@pacbell.net Wed May 11 15:54:15 1994 Path: ashpoly!bigsur!pacrim!krgate!eunha!pacbell!fchoi From: fchoi@pacbell.net (Fiona Choi) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994May11.155415.4251@pacbell.net> Date: Wed, 11 May 1994 15:54:15 GMT Organization: Pacific Bell Internet Services NNTP-Posting-Host: pacbell.net X-Newsreader: TIN [version 1.2 PL2] Lines: 10 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Fiona Choi Tape trading list upon request. SASE required for international mail. From lpopov@unam.mx Thu May 12 16:16:15 1994 Path: ashpoly!cascade!transat!ukc!fennimore!unam!lpopov From: lpopov@unam.mx (Lisa Popov) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994May12.161615.7582@unam.mx> Date: Thu, 12 May 1994 16:16:15 GMT References: <1994May11.155415.4251@pacbell.net> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: Netscape 1.1N Lines: 11 In article <1994May11.155415.4251@pacbell.net>, fchoi@pacbell.net (Fiona Choi) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Lisa Popov US Robotics Courier V.34 @ 33,600 bps "5 sigma is a discovery. 7 is a question." From dnilsson@illinois.edu Sat May 14 04:57:15 1994 Path: ashpoly!bigsur!pacrim!krgate!eunha!illinois!dnilsson From: dnilsson@illinois.edu (Diego Nilsson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994May14.045715.6657@illinois.edu> Date: Sat, 14 May 1994 04:57:15 GMT References: <1994May11.155415.4251@pacbell.net> <1994May12.161615.7582@unam.mx> Organization: University of Illinois Urbana-Champaign NNTP-Posting-Host: illinois.edu X-Newsreader: Netscape 1.1N Lines: 10 In article <1994May12.161615.7582@unam.mx>, lpopov@unam.mx (Lisa Popov) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. -- Diego Nilsson Opinions expressed are solely my own and not those of University of Illinois Urbana-Champaign. ------------------------------------------------------------ From klaurent@cern.ch Mon May 16 07:37:15 1994 Path: ashpoly!bigsur!pacrim!jpgate!kamome!cern!klaurent From: klaurent@cern.ch (Kirsty Laurent) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994May16.073715.6306@cern.ch> Date: Mon, 16 May 1994 07:37:15 GMT References: <1994May11.155415.4251@pacbell.net> <1994May12.161615.7582@unam.mx> <1994May14.045715.6657@illinois.edu> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1994May14.045715.6657@illinois.edu>, dnilsson@illinois.edu (Diego Nilsson) writes: > Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. Netscape 1.1 crashes when loading large preformatted text. Stick to rn or tin! -- Kirsty Laurent Tape trading list upon request. SASE required for international mail. From mjohansson@titech.ac.jp Mon May 16 12:37:15 1994 Path: ashpoly!cascade!transat!ukc!fennimore!titech!mjohansson From: mjohansson@titech.ac.jp (Marta Johansson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994May16.123715.3563@titech.ac.jp> Date: Mon, 16 May 1994 12:37:15 GMT References: <1994May11.155415.4251@pacbell.net> <1994May12.161615.7582@unam.mx> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: Netscape 1.1N Lines: 12 In article <1994May12.161615.7582@unam.mx>, lpopov@unam.mx (Lisa Popov) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Marta Johansson | mjohansson@titech.ac.jp PGP Key fingerprint: 6920 61E4 D4D2 1CD0 "Keep the channels open."