From jlarsson@titech.ac.jp Fri Sep 09 13:25:35 1994
Path: ashpoly!bigsur!pacrim!jpgate!kamome!titech!jlarsson
From: jlarsson@titech.ac.jp (Ji-woo Larsson)
Newsgroups: comp.sys.m68k
Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Sep09.132535.1665@titech.ac.jp>
Date: Fri, 09 Sep 1994 13:25:35 GMT
Organization: Tokyo Institute of Technology Computer Centre
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.
The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket?

-- 
Ji-woo Larsson
Opinions expressed are solely my own and not those of Tokyo Institute of Technology Computer Centre.
------------------------------------------------------------

From mwatanabe@netcom.com Sun Sep 11 09:09:35 1994
Path: ashpoly!cascade!bigsur!netcom!mwatanabe
From: mwatanabe@netcom.com (Mike Watanabe)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Sep11.090935.3507@netcom.com>
Date: Sun, 11 Sep 1994 09:09:35 GMT
References: <1994Sep09.132535.1665@titech.ac.jp>
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In article <1994Sep09.132535.1665@titech.ac.jp>, jlarsson@titech.ac.jp (Ji-woo Larsson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen.

-- 
Mike Watanabe
Tape trading list upon request. SASE required for international mail.

From ksokolov@mit.edu Sun Sep 11 20:28:35 1994
Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!ksokolov
From: ksokolov@mit.edu (Kirsty Sokolov)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Sep11.202835.9383@mit.edu>
Date: Sun, 11 Sep 1994 20:28:35 GMT
References: <1994Sep09.132535.1665@titech.ac.jp>
Organization: Massachusetts Institute of Technology
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In article <1994Sep09.132535.1665@titech.ac.jp>, jlarsson@titech.ac.jp (Ji-woo Larsson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
=== Kirsty Sokolov ===
Dept of Electrical Engineering, Massachusetts Institute of Technology
"Do not worship the copy."

From dsuzuki@u-tokyo.ac.jp Tue Sep 13 04:07:35 1994
Path: ashpoly!cascade!bigsur!u-tokyo!dsuzuki
From: dsuzuki@u-tokyo.ac.jp (Dmitri Suzuki)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Sep13.040735.1676@u-tokyo.ac.jp>
Date: Tue, 13 Sep 1994 04:07:35 GMT
References: <1994Sep09.132535.1665@titech.ac.jp> <1994Sep11.090935.3507@netcom.com>
Organization: University of Tokyo Department of Information Science
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In article <1994Sep11.090935.3507@netcom.com>, mwatanabe@netcom.com (Mike Watanabe) writes:
> Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

-- 
Dmitri Suzuki
Tape trading list upon request. SASE required for international mail.