From asato@clari.net Fri Apr 21 22:25:55 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!clari!asato From: asato@clari.net (Astrid Sato) Newsgroups: comp.sys.m68k Subject: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr21.222555.7553@clari.net> Date: Fri, 21 Apr 1995 22:25:55 GMT Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: Netscape 1.1N Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Astrid Sato "Do not worship the copy." Mac IIci / 68882 FPU / AmigaOS 3.1 From cnakamura@clari.net Sun Apr 23 16:50:55 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!clari!cnakamura From: cnakamura@clari.net (Callum Nakamura) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr23.165055.7283@clari.net> Date: Sun, 23 Apr 1995 16:50:55 GMT References: <1995Apr21.222555.7553@clari.net> Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1995Apr21.222555.7553@clari.net>, asato@clari.net (Astrid Sato) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Callum Nakamura Tape trading list upon request. SASE required for international mail. From bcampbell@pipeline.com Mon Apr 24 08:13:55 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!pipeline!bcampbell From: bcampbell@pipeline.com (Bastien Campbell) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr24.081355.3955@pipeline.com> Date: Mon, 24 Apr 1995 08:13:55 GMT References: <1995Apr21.222555.7553@clari.net> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: Netscape 1.1N Lines: 11 In article <1995Apr21.222555.7553@clari.net>, asato@clari.net (Astrid Sato) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. If you are posting from AOL, please read RFC 1036 before posting again. -- Bastien Campbell *PLONK* filter active for trolls. Sun SparcStation 20 - NetBSD 1.0