From tito@inria.fr Wed Sep 18 15:32:42 1996 Path: ashpoly!cascade!transat!ukc!fennimore!inria!tito From: tito@inria.fr (Tyler Ito) Newsgroups: comp.sys.m68k Subject: Observation: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Sep18.153242.7406@inria.fr> Date: Wed, 18 Sep 1996 15:32:42 GMT Organization: INRIA Rocquencourt NNTP-Posting-Host: inria.fr X-Newsreader: WinVN 0.99.5 Lines: 11 Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Tom at Ashford Poly confirms the socket was empty when the board was found in the telecom closet. -- Tyler Ito *PLONK* filter active for trolls. NeXTstation Turbo Color - NetBSD 1.0 From rwatanabe@netcom.com Fri Sep 20 13:11:42 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!netcom!rwatanabe From: rwatanabe@netcom.com (Raj Watanabe) Newsgroups: comp.sys.m68k Subject: Re: Observation: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Sep20.131142.8074@netcom.com> Date: Fri, 20 Sep 1996 13:11:42 GMT References: <1996Sep18.153242.7406@inria.fr> Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1996Sep18.153242.7406@inria.fr>, tito@inria.fr (Tyler Ito) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack! -- Raj Watanabe "The hatch is open. Is anyone listening?" Pentium 90 (OS/2 Warp) / SunOS 4.1.4