From mtakahashi@demon.co.uk Mon May 06 19:31:05 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!demon!mtakahashi From: mtakahashi@demon.co.uk (Min-jun Takahashi) Newsgroups: comp.sys.m68k Subject: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May06.193105.6693@demon.co.uk> Date: Mon, 06 May 1996 19:31:05 GMT Organization: Demon Internet Services UK NNTP-Posting-Host: demon.co.uk X-Newsreader: WinVN 0.99.5 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Min-jun Takahashi Opinions expressed are solely my own and not those of Demon Internet Services UK. ------------------------------------------------------------ From asantos@illinois.edu Wed May 08 07:12:05 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!illinois!asantos From: asantos@illinois.edu (Anton Santos) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May08.071205.8763@illinois.edu> Date: Wed, 08 May 1996 07:12:05 GMT References: <1996May06.193105.6693@demon.co.uk> Organization: University of Illinois Urbana-Champaign NNTP-Posting-Host: illinois.edu X-Newsreader: Netscape 1.1N Lines: 9 In article <1996May06.193105.6693@demon.co.uk>, mtakahashi@demon.co.uk (Min-jun Takahashi) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Anton Santos *PLONK* filter active for trolls. Amiga 3000T - NetBSD 1.0 From hmacdonald@pacbell.net Wed May 08 13:25:05 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!pacbell!hmacdonald From: hmacdonald@pacbell.net (Hana MacDonald) Newsgroups: comp.sys.m68k Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May08.132505.9523@pacbell.net> Date: Wed, 08 May 1996 13:25:05 GMT References: <1996May06.193105.6693@demon.co.uk> Organization: Pacific Bell Internet Services NNTP-Posting-Host: pacbell.net X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1996May06.193105.6693@demon.co.uk>, mtakahashi@demon.co.uk (Min-jun Takahashi) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. If you are posting from AOL, please read RFC 1036 before posting again. -- Hana MacDonald | hmacdonald@pacbell.net PGP Key fingerprint: F4E0 6EB2 CBE6 F104 "Keep the channels open."