From bandersson@tum.de Tue Jun 28 19:58:10 1994 Path: ashpoly!cascade!transat!ukc!fennimore!tum!bandersson From: bandersson@tum.de (Bruno Andersson) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Jun28.195810.5214@tum.de> Date: Tue, 28 Jun 1994 19:58:10 GMT Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Bruno Andersson Zyxel U-1496E @ 14,400 bps "Row 14. No joke." From kkang@berkeley.edu Thu Jun 30 20:34:10 1994 Path: ashpoly!cascade!transat!sunet!nordrelay!berkeley!kkang From: kkang@berkeley.edu (Kenji Kang) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Jun30.203410.3857@berkeley.edu> Date: Thu, 30 Jun 1994 20:34:10 GMT References: <1994Jun28.195810.5214@tum.de> Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: Netscape 1.1N Lines: 8 In article <1994Jun28.195810.5214@tum.de>, bandersson@tum.de (Bruno Andersson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire). -- Kenji Kang Tape trading list upon request. SASE required for international mail. From lkuznetsov@mit.edu Sat Jul 02 20:46:10 1994 Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!lkuznetsov From: lkuznetsov@mit.edu (Lucia Kuznetsov) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Jul02.204610.5723@mit.edu> Date: Sat, 02 Jul 1994 20:46:10 GMT References: <1994Jun28.195810.5214@tum.de> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1994Jun28.195810.5214@tum.de>, bandersson@tum.de (Bruno Andersson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. -- Lucia Kuznetsov Tape trading list upon request. SASE required for international mail.