From ahughes@earthlink.net Fri Apr 28 18:37:01 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!earthlink!ahughes From: ahughes@earthlink.net (Amy Hughes) Newsgroups: comp.sys.m68k Subject: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr28.183701.7832@earthlink.net> Date: Fri, 28 Apr 1995 18:37:01 GMT Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- === Amy Hughes === Dept of Electrical Engineering, EarthLink Network "We don't sign stars. We build them." From istewart@kth.se Sun Apr 30 21:04:01 1995 Path: ashpoly!cascade!mxgate!coyoacan!kth!istewart From: istewart@kth.se (Ines Stewart) Newsgroups: comp.sys.m68k Subject: Re: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr30.210401.3929@kth.se> Date: Sun, 30 Apr 1995 21:04:01 GMT References: <1995Apr28.183701.7832@earthlink.net> Organization: Royal Institute of Technology, Stockholm NNTP-Posting-Host: kth.se X-Newsreader: Netscape 1.1N Lines: 10 In article <1995Apr28.183701.7832@earthlink.net>, ahughes@earthlink.net (Amy Hughes) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Netscape 1.1 crashes when loading large preformatted text. Stick to rn or tin! -- Ines Stewart Tape trading list upon request. SASE required for international mail.