From tnovak@cmu.edu Fri Feb 23 23:31:34 1996 Path: ashpoly!cascade!bigsur!cmu!tnovak From: tnovak@cmu.edu (Takeshi Novak) Newsgroups: comp.sys.m68k Subject: Data: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Feb23.233134.6166@cmu.edu> Date: Fri, 23 Feb 1996 23:31:34 GMT Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Does anyone have a 27C256 EPROM marked 'MH-U14' or 'ORION-CRYPTO'? -- Takeshi Novak Opinions expressed are solely my own and not those of Carnegie Mellon University School of CS. ------------------------------------------------------------ From lsilva@uu.net Sun Feb 25 08:04:34 1996 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!uu!lsilva From: lsilva@uu.net (Liam Silva) Newsgroups: comp.sys.m68k Subject: Re: Data: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Feb25.080434.3286@uu.net> Date: Sun, 25 Feb 1996 08:04:34 GMT References: <1996Feb23.233134.6166@cmu.edu> Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Feb23.233134.6166@cmu.edu>, tnovak@cmu.edu (Takeshi Novak) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack! -- Liam Silva *PLONK* filter active for trolls. Acorn RiscPC 600 - NetBSD 1.0