From dbrennan@panix.com Sat Dec 21 12:23:21 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!panix!dbrennan From: dbrennan@panix.com (Dmitri Brennan) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec21.122321.1552@panix.com> Date: Sat, 21 Dec 1996 12:23:21 GMT Organization: Public Access Unix of New York NNTP-Posting-Host: panix.com X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Dmitri Brennan Opinions expressed are solely my own and not those of Public Access Unix of New York. ------------------------------------------------------------ From mtakahashi@panix.com Sat Dec 21 14:47:21 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!panix!mtakahashi From: mtakahashi@panix.com (Mike Takahashi) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec21.144721.5354@panix.com> Date: Sat, 21 Dec 1996 14:47:21 GMT References: <1996Dec21.122321.1552@panix.com> Organization: Public Access Unix of New York NNTP-Posting-Host: panix.com X-Newsreader: TIN [version 1.2 PL2] Lines: 11 In article <1996Dec21.122321.1552@panix.com>, dbrennan@panix.com (Dmitri Brennan) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. PGP Public key available via finger or upon request. -- Mike Takahashi *PLONK* filter active for trolls. NeXTstation Turbo Color - NetBSD 1.0 From mweber@unam.mx Mon Dec 23 06:26:21 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!unam!mweber From: mweber@unam.mx (Matthias Weber) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec23.062621.4658@unam.mx> Date: Mon, 23 Dec 1996 06:26:21 GMT References: <1996Dec21.122321.1552@panix.com> <1996Dec21.144721.5354@panix.com> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: Netscape 1.1N Lines: 9 In article <1996Dec21.144721.5354@panix.com>, mtakahashi@panix.com (Mike Takahashi) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Matthias Weber | mweber@unam.mx PGP Key fingerprint: F1BB 7628 3A0B BCA3 "Keep the channels open." From fvasiliev@ox.ac.uk Mon Dec 23 12:21:21 1996 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!ox!fvasiliev From: fvasiliev@ox.ac.uk (Fiona Vasiliev) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec23.122121.4482@ox.ac.uk> Date: Mon, 23 Dec 1996 12:21:21 GMT References: <1996Dec21.122321.1552@panix.com> <1996Dec21.144721.5354@panix.com> Organization: Oxford University Computing Laboratory NNTP-Posting-Host: ox.ac.uk X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1996Dec21.144721.5354@panix.com>, mtakahashi@panix.com (Mike Takahashi) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > PGP Public key available via finger or upon request. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- === Fiona Vasiliev === Dept of Electrical Engineering, Oxford University Computing Laboratory "In theory there is no difference between theory and practice."