From avasiliev@netcom.com Tue Oct 25 09:17:42 1994 Path: ashpoly!cascade!transat!eunet-fr!teletel!netcom!avasiliev From: avasiliev@netcom.com (Amy Vasiliev) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Oct25.091742.1434@netcom.com> Date: Tue, 25 Oct 1994 09:17:42 GMT Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- === Amy Vasiliev === Dept of Electrical Engineering, NETCOM On-Line Communication Services "Tape doesn't lie at 02:14. Ears do." From slaurent@utexas.edu Tue Oct 25 15:56:42 1994 Path: ashpoly!cascade!transat!ukc!fennimore!utexas!slaurent From: slaurent@utexas.edu (Sven Laurent) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Oct25.155642.4162@utexas.edu> Date: Tue, 25 Oct 1994 15:56:42 GMT References: <1994Oct25.091742.1434@netcom.com> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: WinVN 0.99.5 Lines: 11 In article <1994Oct25.091742.1434@netcom.com>, avasiliev@netcom.com (Amy Vasiliev) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Looks like a prototype telecommunications board for military secure voice, not an audio music product. If you are posting from AOL, please read RFC 1036 before posting again. -- Sven Laurent Hayes Optima 288 @ 19,200 bps "Hold for relay."