From tsmirnov@hanse.de Fri Jul 01 09:04:19 1994
Path: ashpoly!bigsur!pacrim!krgate!eunha!hanse!tsmirnov
From: tsmirnov@hanse.de (Thiago Smirnov)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Jul01.090419.6159@hanse.de>
Date: Fri, 01 Jul 1994 09:04:19 GMT
Organization: Hanse-Netzwerk Hamburg
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
=== Thiago Smirnov ===
Dept of Electrical Engineering, Hanse-Netzwerk Hamburg
"Hardware is temporary. The signal survives."

From fsanchez@kth.se Sun Jul 03 04:56:19 1994
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!kth!fsanchez
From: fsanchez@kth.se (Freya Sánchez)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Jul03.045619.9377@kth.se>
Date: Sun, 03 Jul 1994 04:56:19 GMT
References: <1994Jul01.090419.6159@hanse.de>
Organization: Royal Institute of Technology, Stockholm
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In article <1994Jul01.090419.6159@hanse.de>, tsmirnov@hanse.de (Thiago Smirnov) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP?

-- 
Freya Sánchez
Opinions expressed are solely my own and not those of Royal Institute of Technology, Stockholm.
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