From achoi@uu.net Wed Aug 09 02:18:31 1995
Path: ashpoly!cascade!brgate!saturno!uu!achoi
From: achoi@uu.net (Anton Choi)
Newsgroups: comp.sys.m68k
Subject: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Aug09.021831.4981@uu.net>
Date: Wed, 09 Aug 1995 02:18:31 GMT
Organization: UUNET Technologies, Falls Church VA
NNTP-Posting-Host: uu.net
X-Newsreader: Netscape 1.1N
Lines: 11

Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.

The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.
Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF.

Did Marcus take the decryption EPROM with him when he left the lab?

-- 
=== Anton Choi ===
Dept of Electrical Engineering, UUNET Technologies, Falls Church VA
"5 sigma is a discovery. 7 is a question."

From awatanabe@utexas.edu Fri Aug 11 04:52:31 1995
Path: ashpoly!bigsur!pacrim!jpgate!kamome!utexas!awatanabe
From: awatanabe@utexas.edu (Andrei Watanabe)
Newsgroups: comp.sys.m68k
Subject: Re: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Aug11.045231.1453@utexas.edu>
Date: Fri, 11 Aug 1995 04:52:31 GMT
References: <1995Aug09.021831.4981@uu.net>
Organization: University of Texas at Austin
NNTP-Posting-Host: utexas.edu
X-Newsreader: Netscape 1.1N
Lines: 10

In article <1995Aug09.021831.4981@uu.net>, achoi@uu.net (Anton Choi) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984.

-- 
Andrei Watanabe | awatanabe@utexas.edu
PGP Key fingerprint: 3A2A 7F73 B5F6 97C5
"Keep the channels open."

From rstewart@hanse.de Fri Aug 11 12:49:31 1995
Path: ashpoly!cascade!transat!eunet-de!hansebox!hanse!rstewart
From: rstewart@hanse.de (Raj Stewart)
Newsgroups: comp.sys.m68k
Subject: Re: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Aug11.124931.1169@hanse.de>
Date: Fri, 11 Aug 1995 12:49:31 GMT
References: <1995Aug09.021831.4981@uu.net>
Organization: Hanse-Netzwerk Hamburg
NNTP-Posting-Host: hanse.de
X-Newsreader: Netscape 1.1N
Lines: 8

In article <1995Aug09.021831.4981@uu.net>, achoi@uu.net (Anton Choi) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.

Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984.

-- 
Raj Stewart
Tape trading list upon request. SASE required for international mail.

From emoreno@cam.ac.uk Sun Aug 13 07:08:31 1995
Path: ashpoly!cascade!transat!ukc!fennimore!cam!emoreno
From: emoreno@cam.ac.uk (Élodie Moreno)
Newsgroups: comp.sys.m68k
Subject: Re: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Aug13.070831.4510@cam.ac.uk>
Date: Sun, 13 Aug 1995 07:08:31 GMT
References: <1995Aug09.021831.4981@uu.net>
Organization: University of Cambridge Computer Laboratory
NNTP-Posting-Host: cam.ac.uk
X-Newsreader: TIN [version 1.2 PL2]
Lines: 9

In article <1995Aug09.021831.4981@uu.net>, achoi@uu.net (Anton Choi) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack!

-- 
Élodie Moreno
Tape trading list upon request. SASE required for international mail.