From bramirez@inria.fr Fri Apr 21 23:52:08 1995
Path: ashpoly!cascade!bigsur!inria!bramirez
From: bramirez@inria.fr (Brian Ramírez)
Newsgroups: comp.sys.m68k
Subject: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Apr21.235208.3131@inria.fr>
Date: Fri, 21 Apr 1995 23:52:08 GMT
Organization: INRIA Rocquencourt
NNTP-Posting-Host: inria.fr
X-Newsreader: NewsWatcher 2.0b24
Lines: 11

Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.

The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.
Without U14, the board can track the 14.2 Hz carrier, but cannot descramble the binary payload of Nodes 11 through 14.

Does anyone have a 27C256 EPROM marked 'MH-U14' or 'ORION-CRYPTO'?

-- 
=== Brian Ramírez ===
Dept of Electrical Engineering, INRIA Rocquencourt
"Hardware is temporary. The signal survives."

From fvasiliev@unam.mx Sun Apr 23 16:14:08 1995
Path: ashpoly!cascade!transat!sunet!nordrelay!unam!fvasiliev
From: fvasiliev@unam.mx (Fiona Vasiliev)
Newsgroups: comp.sys.m68k
Subject: Re: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Apr23.161408.8598@unam.mx>
Date: Sun, 23 Apr 1995 16:14:08 GMT
References: <1995Apr21.235208.3131@inria.fr>
Organization: Universidad Nacional Autónoma de México (DGSCA)
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In article <1995Apr21.235208.3131@inria.fr>, bramirez@inria.fr (Brian Ramírez) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

That's why Line 08 says: 'WHEN EVERY NODE IS WHOLE, THE CHANNEL OPENS.' It requires all physical keys.

Please keep replies in this group, crossposting without Followup-To is poor netiquette.

-- 
Fiona Vasiliev
Tape trading list upon request. SASE required for international mail.

From bsilva@kth.se Mon Apr 24 03:39:08 1995
Path: ashpoly!cascade!transat!eunet-fr!teletel!kth!bsilva
From: bsilva@kth.se (Bill Silva)
Newsgroups: comp.sys.m68k
Subject: Re: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995Apr24.033908.3389@kth.se>
Date: Mon, 24 Apr 1995 03:39:08 GMT
References: <1995Apr21.235208.3131@inria.fr>
Organization: Royal Institute of Technology, Stockholm
NNTP-Posting-Host: kth.se
X-Newsreader: TIN [version 1.2 PL2]
Lines: 10

In article <1995Apr21.235208.3131@inria.fr>, bramirez@inria.fr (Brian Ramírez) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984.

-- 
=== Bill Silva ===
Dept of Electrical Engineering, Royal Institute of Technology, Stockholm
"Row 14. No joke."