From iwatanabe@delphi.com Wed Nov 01 18:00:33 1995
Path: ashpoly!cascade!transat!sunet!nordrelay!delphi!iwatanabe
From: iwatanabe@delphi.com (Ines Watanabe)
Newsgroups: comp.sys.m68k
Subject: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Nov01.180033.7927@delphi.com>
Date: Wed, 01 Nov 1995 18:00:33 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Ines Watanabe
Opinions expressed are solely my own and not those of Delphi Internet Services.
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From cpetrov@purdue.edu Thu Nov 02 04:01:33 1995
Path: ashpoly!cascade!transat!sunet!nordrelay!purdue!cpetrov
From: cpetrov@purdue.edu (Callum Petrov)
Newsgroups: comp.sys.m68k
Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Nov02.040133.4352@purdue.edu>
Date: Thu, 02 Nov 1995 04:01:33 GMT
References: <1995Nov01.180033.7927@delphi.com>
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In article <1995Nov01.180033.7927@delphi.com>, iwatanabe@delphi.com (Ines Watanabe) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

My 14.4k connection dropped twice trying to fetch this thread. Keep articles concise!

-- 
Callum Petrov | cpetrov@purdue.edu
PGP Key fingerprint: BEE8 A701 FABB C700
"Keep the channels open."