From smacdonald@mit.edu Mon Sep 18 09:09:30 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!mit!smacdonald From: smacdonald@mit.edu (Sven MacDonald) Newsgroups: comp.sys.m68k Subject: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep18.090930.1082@mit.edu> Date: Mon, 18 Sep 1995 09:09:30 GMT Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Sven MacDonald Zyxel U-1496E @ 28,800 bps "The hatch is open. Is anyone listening?" From rtanaka@cern.ch Tue Sep 19 06:53:30 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!cern!rtanaka From: rtanaka@cern.ch (Renata Tanaka) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep19.065330.9409@cern.ch> Date: Tue, 19 Sep 1995 06:53:30 GMT References: <1995Sep18.090930.1082@mit.edu> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1995Sep18.090930.1082@mit.edu>, smacdonald@mit.edu (Sven MacDonald) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Renata Tanaka "There are 14 nodes and only 10 countries. Count again." Acorn RiscPC 600 / FreeBSD 2.1