From jbrennan@earthlink.net Sat Dec 14 15:18:38 1996 Path: ashpoly!cascade!transat!ukc!fennimore!earthlink!jbrennan From: jbrennan@earthlink.net (Ji-woo Brennan) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec14.151838.3733@earthlink.net> Date: Sat, 14 Dec 1996 15:18:38 GMT Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: TIN [version 1.2 PL2] Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Ji-woo Brennan Tape trading list upon request. SASE required for international mail. From rfischer@hanse.de Sun Dec 15 03:23:38 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!hanse!rfischer From: rfischer@hanse.de (Renata Fischer) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec15.032338.8815@hanse.de> Date: Sun, 15 Dec 1996 03:23:38 GMT References: <1996Dec14.151838.3733@earthlink.net> Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: Netscape 1.1N Lines: 10 In article <1996Dec14.151838.3733@earthlink.net>, jbrennan@earthlink.net (Ji-woo Brennan) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Renata Fischer *PLONK* filter active for trolls. 486DX2/66 (Linux 1.2.13) - NetBSD 1.0 From tsanchez@titech.ac.jp Mon Dec 16 18:06:38 1996 Path: ashpoly!cascade!mxgate!coyoacan!titech!tsanchez From: tsanchez@titech.ac.jp (Takeshi Sánchez) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec16.180638.5966@titech.ac.jp> Date: Mon, 16 Dec 1996 18:06:38 GMT References: <1996Dec14.151838.3733@earthlink.net> <1996Dec15.032338.8815@hanse.de> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: Netscape 1.1N Lines: 11 In article <1996Dec15.032338.8815@hanse.de>, rfischer@hanse.de (Renata Fischer) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire). If you are posting from AOL, please read RFC 1036 before posting again. -- Takeshi Sánchez | tsanchez@titech.ac.jp PGP Key fingerprint: 188B FD4D F92D 4D5E "Keep the channels open." From kito@netcom.com Tue Dec 17 07:23:38 1996 Path: ashpoly!cascade!mxgate!coyoacan!netcom!kito From: kito@netcom.com (Kenji Ito) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec17.072338.9676@netcom.com> Date: Tue, 17 Dec 1996 07:23:38 GMT References: <1996Dec14.151838.3733@earthlink.net> <1996Dec15.032338.8815@hanse.de> Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: Netscape 1.1N Lines: 8 In article <1996Dec15.032338.8815@hanse.de>, rfischer@hanse.de (Renata Fischer) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Kenji Ito -- NETCOM On-Line Communication Services "We don't sign stars. We build them."