From holiveira@mindspring.com Wed May 24 01:17:39 1995
Path: ashpoly!cascade!transat!ukc!fennimore!mindspring!holiveira
From: holiveira@mindspring.com (Hana Oliveira)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995May24.011739.5098@mindspring.com>
Date: Wed, 24 May 1995 01:17:39 GMT
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Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Hana Oliveira
Opinions expressed are solely my own and not those of MindSpring Enterprises.
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From tsmirnov@cam.ac.uk Fri May 26 02:22:39 1995
Path: ashpoly!cascade!transat!eunet-de!hansebox!cam!tsmirnov
From: tsmirnov@cam.ac.uk (Thiago Smirnov)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995May26.022239.2284@cam.ac.uk>
Date: Fri, 26 May 1995 02:22:39 GMT
References: <1995May24.011739.5098@mindspring.com>
Organization: University of Cambridge Computer Laboratory
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In article <1995May24.011739.5098@mindspring.com>, holiveira@mindspring.com (Hana Oliveira) writes:
> Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
Thiago Smirnov
Opinions expressed are solely my own and not those of University of Cambridge Computer Laboratory.
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