From lsouza@cern.ch Tue May 23 16:24:35 1995
Path: ashpoly!cascade!brgate!saturno!cern!lsouza
From: lsouza@cern.ch (Lucia Souza)
Newsgroups: comp.sys.m68k
Subject: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995May23.162435.3110@cern.ch>
Date: Tue, 23 May 1995 16:24:35 GMT
Organization: European Laboratory for Particle Physics, Geneva
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Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.

The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.
Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF.

Did Marcus take the decryption EPROM with him when he left the lab?

-- 
Lucia Souza -- European Laboratory for Particle Physics, Geneva
"Hardware is temporary. The signal survives."

From osato@demon.co.uk Thu May 25 14:35:35 1995
Path: ashpoly!cascade!brgate!saturno!demon!osato
From: osato@demon.co.uk (Olga Sato)
Newsgroups: comp.sys.m68k
Subject: Re: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995May25.143535.7617@demon.co.uk>
Date: Thu, 25 May 1995 14:35:35 GMT
References: <1995May23.162435.3110@cern.ch>
Organization: Demon Internet Services UK
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In article <1995May23.162435.3110@cern.ch>, lsouza@cern.ch (Lucia Souza) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984.

Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns.

-- 
Olga Sato
Tape trading list upon request. SASE required for international mail.

From spetrov@demon.co.uk Sat May 27 16:12:35 1995
Path: ashpoly!cascade!transat!eunet-fr!teletel!demon!spetrov
From: spetrov@demon.co.uk (Seo-yeon Petrov)
Newsgroups: comp.sys.m68k
Subject: Re: Discussion: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1995May27.161235.7901@demon.co.uk>
Date: Sat, 27 May 1995 16:12:35 GMT
References: <1995May23.162435.3110@cern.ch>
Organization: Demon Internet Services UK
NNTP-Posting-Host: demon.co.uk
X-Newsreader: WinVN 0.99.5
Lines: 12

In article <1995May23.162435.3110@cern.ch>, lsouza@cern.ch (Lucia Souza) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984.

Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns.

-- 
=== Seo-yeon Petrov ===
Dept of Electrical Engineering, Demon Internet Services UK
"Tape doesn't lie at 02:14. Ears do."