From mnovak@uu.net Sat Sep 16 10:58:52 1995 Path: ashpoly!cascade!transat!ukc!fennimore!uu!mnovak From: mnovak@uu.net (Matthias Novak) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep16.105852.8943@uu.net> Date: Sat, 16 Sep 1995 10:58:52 GMT Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: WinVN 0.99.5 Lines: 11 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- === Matthias Novak === Dept of Electrical Engineering, UUNET Technologies, Falls Church VA "The hatch is open. Is anyone listening?" From dnilsson@pipeline.com Sat Sep 16 18:02:52 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!pipeline!dnilsson From: dnilsson@pipeline.com (Dong-hyun Nilsson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep16.180252.9066@pipeline.com> Date: Sat, 16 Sep 1995 18:02:52 GMT References: <1995Sep16.105852.8943@uu.net> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: WinVN 0.99.5 Lines: 11 In article <1995Sep16.105852.8943@uu.net>, mnovak@uu.net (Matthias Novak) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. PGP Public key available via finger or upon request. -- Dong-hyun Nilsson Hayes Optima 288 @ 19,200 bps "Row 14. No joke." From sgarcia@cern.ch Sun Sep 17 10:23:52 1995 Path: ashpoly!cascade!brgate!saturno!cern!sgarcia From: sgarcia@cern.ch (Seo-yeon García) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep17.102352.9285@cern.ch> Date: Sun, 17 Sep 1995 10:23:52 GMT References: <1995Sep16.105852.8943@uu.net> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: Netscape 1.1N Lines: 10 In article <1995Sep16.105852.8943@uu.net>, mnovak@uu.net (Matthias Novak) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. PGP Public key available via finger or upon request. -- Seo-yeon García Tape trading list upon request. SASE required for international mail. From bpetrov@pipeline.com Sun Sep 17 18:16:52 1995 Path: ashpoly!cascade!transat!eunet-fr!teletel!pipeline!bpetrov From: bpetrov@pipeline.com (Bill Petrov) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep17.181652.2046@pipeline.com> Date: Sun, 17 Sep 1995 18:16:52 GMT References: <1995Sep16.105852.8943@uu.net> <1995Sep17.102352.9285@cern.ch> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1995Sep17.102352.9285@cern.ch>, sgarcia@cern.ch (Seo-yeon García) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > PGP Public key available via finger or upon request. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Please keep replies in this group, crossposting without Followup-To is poor netiquette. -- Bill Petrov Tape trading list upon request. SASE required for international mail.