From shughes@kth.se Fri Jan 12 05:42:10 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!kth!shughes From: shughes@kth.se (Sun-mi Hughes) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan12.054210.5069@kth.se> Date: Fri, 12 Jan 1996 05:42:10 GMT Organization: Royal Institute of Technology, Stockholm NNTP-Posting-Host: kth.se X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Sun-mi Hughes | shughes@kth.se PGP Key fingerprint: A37C 3953 9CBF 1675 "Keep the channels open." From smartinez@kiae.su Fri Jan 12 12:24:10 1996 Path: ashpoly!cascade!brgate!saturno!kiae!smartinez From: smartinez@kiae.su (Steve Martínez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan12.122410.8103@kiae.su> Date: Fri, 12 Jan 1996 12:24:10 GMT References: <1996Jan12.054210.5069@kth.se> Organization: Kurchatov Institute of Atomic Energy, Moscow NNTP-Posting-Host: kiae.su X-Newsreader: TIN [version 1.2 PL2] Lines: 11 In article <1996Jan12.054210.5069@kth.se>, shughes@kth.se (Sun-mi Hughes) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- === Steve Martínez === Dept of Electrical Engineering, Kurchatov Institute of Atomic Energy, Moscow "Measuring a record you own is listening, not piracy." From slarsson@unam.mx Sat Jan 13 16:19:10 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!unam!slarsson From: slarsson@unam.mx (Seo-yeon Larsson) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan13.161910.2123@unam.mx> Date: Sat, 13 Jan 1996 16:19:10 GMT References: <1996Jan12.054210.5069@kth.se> <1996Jan12.122410.8103@kiae.su> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: Netscape 1.1N Lines: 10 In article <1996Jan12.122410.8103@kiae.su>, smartinez@kiae.su (Steve Martínez) writes: > Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Seo-yeon Larsson | slarsson@unam.mx PGP Key fingerprint: E9A9 CF16 6CD5 9AB1 "Keep the channels open." From abrennan@stanford.edu Mon Jan 15 03:19:10 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!stanford!abrennan From: abrennan@stanford.edu (Anja Brennan) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan15.031910.1887@stanford.edu> Date: Mon, 15 Jan 1996 03:19:10 GMT References: <1996Jan12.054210.5069@kth.se> <1996Jan12.122410.8103@kiae.su> <1996Jan13.161910.2123@unam.mx> Organization: Stanford University Computer Systems Lab NNTP-Posting-Host: stanford.edu X-Newsreader: Netscape 1.1N Lines: 9 In article <1996Jan13.161910.2123@unam.mx>, slarsson@unam.mx (Seo-yeon Larsson) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? -- Anja Brennan "5 sigma is a discovery. 7 is a question." NeXTstation Turbo Color / NEXTSTEP 3.3 From trodriguez@rwth-aachen.de Tue Jan 16 22:17:10 1996 Path: ashpoly!cascade!transat!ukc!fennimore!rwth-aachen!trodriguez From: trodriguez@rwth-aachen.de (Tyler Rodríguez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan16.221710.7525@rwth-aachen.de> Date: Tue, 16 Jan 1996 22:17:10 GMT References: <1996Jan12.054210.5069@kth.se> <1996Jan12.122410.8103@kiae.su> Organization: RWTH Aachen Informatik NNTP-Posting-Host: rwth-aachen.de X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Jan12.122410.8103@kiae.su>, smartinez@kiae.su (Steve Martínez) writes: > Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Tyler Rodríguez Hayes Optima 288 @ 33,600 bps "A soul is not exclusive to biology."