From osilva@cmu.edu Thu May 09 13:12:21 1996 Path: ashpoly!cascade!mxgate!coyoacan!cmu!osilva From: osilva@cmu.edu (Olga Silva) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May09.131221.3674@cmu.edu> Date: Thu, 09 May 1996 13:12:21 GMT Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Olga Silva *PLONK* filter active for trolls. PC-9821Ap2 (NEC) - NetBSD 1.0 From ggarcia@mit.edu Thu May 09 17:23:21 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!ggarcia From: ggarcia@mit.edu (Graham García) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May09.172321.2456@mit.edu> Date: Thu, 09 May 1996 17:23:21 GMT References: <1996May09.131221.3674@cmu.edu> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: Netscape 1.1N Lines: 8 In article <1996May09.131221.3674@cmu.edu>, osilva@cmu.edu (Olga Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. -- Graham García Tape trading list upon request. SASE required for international mail. From jrodriguez@ox.ac.uk Fri May 10 06:55:21 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!ox!jrodriguez From: jrodriguez@ox.ac.uk (Ji-woo Rodríguez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May10.065521.7179@ox.ac.uk> Date: Fri, 10 May 1996 06:55:21 GMT References: <1996May09.131221.3674@cmu.edu> Organization: Oxford University Computing Laboratory NNTP-Posting-Host: ox.ac.uk X-Newsreader: WinVN 0.99.5 Lines: 11 In article <1996May09.131221.3674@cmu.edu>, osilva@cmu.edu (Olga Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Ji-woo Rodríguez Opinions expressed are solely my own and not those of Oxford University Computing Laboratory. ------------------------------------------------------------ From bsmirnov@pipeline.com Sun May 12 07:42:21 1996 Path: ashpoly!cascade!brgate!saturno!pipeline!bsmirnov From: bsmirnov@pipeline.com (Bruno Smirnov) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May12.074221.3660@pipeline.com> Date: Sun, 12 May 1996 07:42:21 GMT References: <1996May09.131221.3674@cmu.edu> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1996May09.131221.3674@cmu.edu>, osilva@cmu.edu (Olga Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire). -- Bruno Smirnov "Measuring a record you own is listening, not piracy." Decstation 5000/200 / SunOS 4.1.4 From ltanaka@uni-hamburg.de Mon May 13 22:37:21 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!uni-hamburg!ltanaka From: ltanaka@uni-hamburg.de (Lars Tanaka) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996May13.223721.3118@uni-hamburg.de> Date: Mon, 13 May 1996 22:37:21 GMT References: <1996May09.131221.3674@cmu.edu> <1996May10.065521.7179@ox.ac.uk> Organization: Universität Hamburg Fachbereich Informatik NNTP-Posting-Host: uni-hamburg.de X-Newsreader: Netscape 1.1N Lines: 9 In article <1996May10.065521.7179@ox.ac.uk>, jrodriguez@ox.ac.uk (Ji-woo Rodríguez) writes: > The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Lars Tanaka -- Universität Hamburg Fachbereich Informatik "Marcus is not one man."