From nlindqvist@clari.net Sun Aug 13 07:53:44 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!clari!nlindqvist From: nlindqvist@clari.net (Nadia Lindqvist) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug13.075344.3629@clari.net> Date: Sun, 13 Aug 1995 07:53:44 GMT Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: Netscape 1.1N Lines: 11 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Nadia Lindqvist Hayes Optima 288 @ ISDN 64k bps "Measuring a record you own is listening, not piracy." From egarcia@kiae.su Mon Aug 14 20:40:44 1995 Path: ashpoly!cascade!transat!ukc!fennimore!kiae!egarcia From: egarcia@kiae.su (Elaine García) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug14.204044.5604@kiae.su> Date: Mon, 14 Aug 1995 20:40:44 GMT References: <1995Aug13.075344.3629@clari.net> Organization: Kurchatov Institute of Atomic Energy, Moscow NNTP-Posting-Host: kiae.su X-Newsreader: Netscape 1.1N Lines: 9 In article <1995Aug13.075344.3629@clari.net>, nlindqvist@clari.net (Nadia Lindqvist) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- === Elaine García === Dept of Electrical Engineering, Kurchatov Institute of Atomic Energy, Moscow "Hardware is temporary. The signal survives." From lweber@cmu.edu Wed Aug 16 10:08:44 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!cmu!lweber From: lweber@cmu.edu (Lars Weber) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug16.100844.7545@cmu.edu> Date: Wed, 16 Aug 1995 10:08:44 GMT References: <1995Aug13.075344.3629@clari.net> <1995Aug14.204044.5604@kiae.su> Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 8 In article <1995Aug14.204044.5604@kiae.su>, egarcia@kiae.su (Elaine García) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Lars Weber -- Carnegie Mellon University School of CS "Hold for relay." From leriksson@titech.ac.jp Wed Aug 16 20:51:44 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!titech!leriksson From: leriksson@titech.ac.jp (Liam Eriksson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug16.205144.9714@titech.ac.jp> Date: Wed, 16 Aug 1995 20:51:44 GMT References: <1995Aug13.075344.3629@clari.net> <1995Aug14.204044.5604@kiae.su> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Aug14.204044.5604@kiae.su>, egarcia@kiae.su (Elaine García) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Liam Eriksson SupraFAXModem 28.8 @ 9600 Telebit bps "Tape doesn't lie at 02:14. Ears do."