From lpetrov@titech.ac.jp Sat Oct 07 01:25:01 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!titech!lpetrov From: lpetrov@titech.ac.jp (Liam Petrov) Newsgroups: comp.sys.m68k Subject: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Oct07.012501.9936@titech.ac.jp> Date: Sat, 07 Oct 1995 01:25:01 GMT Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Does anyone have a 27C256 EPROM marked 'MH-U14' or 'ORION-CRYPTO'? -- Liam Petrov "Hold for relay." Commodore Amiga 500 (1MB OCS) / TOS 4.04 From jandersson@mit.edu Sun Oct 08 18:42:01 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!mit!jandersson From: jandersson@mit.edu (Joachim Andersson) Newsgroups: comp.sys.m68k Subject: Re: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Oct08.184201.4799@mit.edu> Date: Sun, 08 Oct 1995 18:42:01 GMT References: <1995Oct07.012501.9936@titech.ac.jp> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1995Oct07.012501.9936@titech.ac.jp>, lpetrov@titech.ac.jp (Liam Petrov) writes: > Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack! -- Joachim Andersson Practical Peripherals 14.4 @ ISDN 64k bps "The carrier frequency does not drift by accident."