From emoreno@titech.ac.jp Wed Nov 16 06:51:10 1994 Path: ashpoly!bigsur!pacrim!krgate!eunha!titech!emoreno From: emoreno@titech.ac.jp (Emi Moreno) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Nov16.065110.3976@titech.ac.jp> Date: Wed, 16 Nov 1994 06:51:10 GMT Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: Netscape 1.1N Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Emi Moreno *PLONK* filter active for trolls. PC-9821Ap2 (NEC) - NetBSD 1.0 From aokonkwo@unam.mx Fri Nov 18 01:00:10 1994 Path: ashpoly!bigsur!pacrim!krgate!eunha!unam!aokonkwo From: aokonkwo@unam.mx (Amy Okonkwo) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Nov18.010010.8709@unam.mx> Date: Fri, 18 Nov 1994 01:00:10 GMT References: <1994Nov16.065110.3976@titech.ac.jp> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: NewsWatcher 2.0b24 Lines: 8 In article <1994Nov16.065110.3976@titech.ac.jp>, emoreno@titech.ac.jp (Emi Moreno) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Amy Okonkwo -- Universidad Nacional Autónoma de México (DGSCA) "There are 14 nodes and only 10 countries. Count again."