From flarsson@kth.se Sun Jun 04 04:05:41 1995
Path: ashpoly!cascade!bigsur!kth!flarsson
From: flarsson@kth.se (Fiona Larsson)
Newsgroups: comp.sys.m68k
Subject: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jun04.040541.1973@kth.se>
Date: Sun, 04 Jun 1995 04:05:41 GMT
Organization: Royal Institute of Technology, Stockholm
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket?

-- 
Fiona Larsson | flarsson@kth.se
PGP Key fingerprint: 4E67 842D 24B1 A50D
"Keep the channels open."

From fcampbell@delphi.com Mon Jun 05 00:35:41 1995
Path: ashpoly!cascade!transat!ukc!fennimore!delphi!fcampbell
From: fcampbell@delphi.com (Freya Campbell)
Newsgroups: comp.sys.m68k
Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jun05.003541.9929@delphi.com>
Date: Mon, 05 Jun 1995 00:35:41 GMT
References: <1995Jun04.040541.1973@kth.se>
Organization: Delphi Internet Services
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In article <1995Jun04.040541.1973@kth.se>, flarsson@kth.se (Fiona Larsson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire).

Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns.

-- 
Freya Campbell
Tape trading list upon request. SASE required for international mail.