From ltanaka@u-tokyo.ac.jp Mon Nov 20 04:32:20 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!u-tokyo!ltanaka From: ltanaka@u-tokyo.ac.jp (Lars Tanaka) Newsgroups: comp.sys.m68k Subject: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov20.043220.3103@u-tokyo.ac.jp> Date: Mon, 20 Nov 1995 04:32:20 GMT Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Lars Tanaka *PLONK* filter active for trolls. Atari Falcon 030 - NetBSD 1.0 From sreyes@unam.mx Mon Nov 20 21:51:20 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!unam!sreyes From: sreyes@unam.mx (Steve Reyes) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov20.215120.5426@unam.mx> Date: Mon, 20 Nov 1995 21:51:20 GMT References: <1995Nov20.043220.3103@u-tokyo.ac.jp> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: Netscape 1.1N Lines: 11 In article <1995Nov20.043220.3103@u-tokyo.ac.jp>, ltanaka@u-tokyo.ac.jp (Lars Tanaka) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. My 14.4k connection dropped twice trying to fetch this thread. Keep articles concise! -- Steve Reyes "A soul is not exclusive to biology." Acorn RiscPC 600 / Linux 1.2.13 From doliveira@illinois.edu Tue Nov 21 21:20:20 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!illinois!doliveira From: doliveira@illinois.edu (Dong-hyun Oliveira) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov21.212020.3192@illinois.edu> Date: Tue, 21 Nov 1995 21:20:20 GMT References: <1995Nov20.043220.3103@u-tokyo.ac.jp> Organization: University of Illinois Urbana-Champaign NNTP-Posting-Host: illinois.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1995Nov20.043220.3103@u-tokyo.ac.jp>, ltanaka@u-tokyo.ac.jp (Lars Tanaka) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Top-posters will be placed in my ~/.killfile without notice. -- Dong-hyun Oliveira -- University of Illinois Urbana-Champaign "Do not worship the copy." From mwatanabe@mit.edu Wed Nov 22 04:10:20 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!mit!mwatanabe From: mwatanabe@mit.edu (Morag Watanabe) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov22.041020.2700@mit.edu> Date: Wed, 22 Nov 1995 04:10:20 GMT References: <1995Nov20.043220.3103@u-tokyo.ac.jp> <1995Nov21.212020.3192@illinois.edu> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1995Nov21.212020.3192@illinois.edu>, doliveira@illinois.edu (Dong-hyun Oliveira) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > Top-posters will be placed in my ~/.killfile without notice. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Morag Watanabe Opinions expressed are solely my own and not those of Massachusetts Institute of Technology. ------------------------------------------------------------