From mmoreno@pipeline.com Tue Aug 09 18:39:33 1994
Path: ashpoly!cascade!transat!sunet!nordrelay!pipeline!mmoreno
From: mmoreno@pipeline.com (Mei Moreno)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Aug09.183933.5360@pipeline.com>
Date: Tue, 09 Aug 1994 18:39:33 GMT
Organization: The Pipeline Internet Network
NNTP-Posting-Host: pipeline.com
X-Newsreader: Netscape 1.1N
Lines: 11

Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.

At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
Mei Moreno
Opinions expressed are solely my own and not those of The Pipeline Internet Network.
------------------------------------------------------------

From jsantos@titech.ac.jp Wed Aug 10 17:46:33 1994
Path: ashpoly!bigsur!pacrim!jpgate!kamome!titech!jsantos
From: jsantos@titech.ac.jp (Jen Santos)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Aug10.174633.6640@titech.ac.jp>
Date: Wed, 10 Aug 1994 17:46:33 GMT
References: <1994Aug09.183933.5360@pipeline.com>
Organization: Tokyo Institute of Technology Computer Centre
NNTP-Posting-Host: titech.ac.jp
X-Newsreader: TIN [version 1.2 PL2]
Lines: 9

In article <1994Aug09.183933.5360@pipeline.com>, mmoreno@pipeline.com (Mei Moreno) writes:
> Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
Jen Santos | jsantos@titech.ac.jp
PGP Key fingerprint: B4D1 CEF1 28DC AE80
"Keep the channels open."