From snakamura@purdue.edu Sun Jul 09 05:01:12 1995 Path: ashpoly!cascade!bigsur!purdue!snakamura From: snakamura@purdue.edu (Sven Nakamura) Newsgroups: comp.sys.m68k Subject: WTB/WTT: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Jul09.050112.2250@purdue.edu> Date: Sun, 09 Jul 1995 05:01:12 GMT Organization: Purdue University Engineering Computer Network NNTP-Posting-Host: purdue.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Does anyone have a 27C256 EPROM marked 'MH-U14' or 'ORION-CRYPTO'? -- Sven Nakamura "We don't sign stars. We build them." Sun SparcStation 20 / System 7.5.1 From tfournier@u-tokyo.ac.jp Sun Jul 09 17:45:12 1995 Path: ashpoly!cascade!transat!ukc!fennimore!u-tokyo!tfournier From: tfournier@u-tokyo.ac.jp (Thiago Fournier) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Jul09.174512.3249@u-tokyo.ac.jp> Date: Sun, 09 Jul 1995 17:45:12 GMT References: <1995Jul09.050112.2250@purdue.edu> Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1995Jul09.050112.2250@purdue.edu>, snakamura@purdue.edu (Sven Nakamura) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Thiago Fournier Hayes Optima 288 @ 28,800 bps "They will send a copy in my place." From knovak@mindspring.com Mon Jul 10 15:28:12 1995 Path: ashpoly!cascade!transat!ukc!fennimore!mindspring!knovak From: knovak@mindspring.com (Katrin Novak) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Jul10.152812.4230@mindspring.com> Date: Mon, 10 Jul 1995 15:28:12 GMT References: <1995Jul09.050112.2250@purdue.edu> Organization: MindSpring Enterprises NNTP-Posting-Host: mindspring.com X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1995Jul09.050112.2250@purdue.edu>, snakamura@purdue.edu (Sven Nakamura) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984. -- Katrin Novak -- MindSpring Enterprises "When every node is whole, the channel opens." From rsouza@rwth-aachen.de Wed Jul 12 04:24:12 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!rwth-aachen!rsouza From: rsouza@rwth-aachen.de (Raj Souza) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Jul12.042412.7219@rwth-aachen.de> Date: Wed, 12 Jul 1995 04:24:12 GMT References: <1995Jul09.050112.2250@purdue.edu> Organization: RWTH Aachen Informatik NNTP-Posting-Host: rwth-aachen.de X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Jul09.050112.2250@purdue.edu>, snakamura@purdue.edu (Sven Nakamura) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984. -- Raj Souza Zyxel U-1496E @ 14,400 bps "Marcus is not one man."