From nhernandez@purdue.edu Sun Jun 25 03:58:08 1995 Path: ashpoly!cascade!transat!ukc!fennimore!purdue!nhernandez From: nhernandez@purdue.edu (Nadine Hernández) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jun25.035808.2779@purdue.edu> Date: Sun, 25 Jun 1995 03:58:08 GMT Organization: Purdue University Engineering Computer Network NNTP-Posting-Host: purdue.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- === Nadine Hernández === Dept of Electrical Engineering, Purdue University Engineering Computer Network "In theory there is no difference between theory and practice." From nnovak@uu.net Mon Jun 26 06:44:08 1995 Path: ashpoly!cascade!bigsur!uu!nnovak From: nnovak@uu.net (Nadine Novak) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jun26.064408.7615@uu.net> Date: Mon, 26 Jun 1995 06:44:08 GMT References: <1995Jun25.035808.2779@purdue.edu> Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Jun25.035808.2779@purdue.edu>, nhernandez@purdue.edu (Nadine Hernández) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Nadine Novak Opinions expressed are solely my own and not those of UUNET Technologies, Falls Church VA. ------------------------------------------------------------ From kkuznetsov@titech.ac.jp Wed Jun 28 08:33:08 1995 Path: ashpoly!cascade!bigsur!titech!kkuznetsov From: kkuznetsov@titech.ac.jp (Kenji Kuznetsov) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jun28.083308.9446@titech.ac.jp> Date: Wed, 28 Jun 1995 08:33:08 GMT References: <1995Jun25.035808.2779@purdue.edu> <1995Jun26.064408.7615@uu.net> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: WinVN 0.99.5 Lines: 11 In article <1995Jun26.064408.7615@uu.net>, nnovak@uu.net (Nadine Novak) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. Unsubscribe me from this list! (Wait, this is Usenet, never mind). -- Kenji Kuznetsov Opinions expressed are solely my own and not those of Tokyo Institute of Technology Computer Centre. ------------------------------------------------------------ From asato@rwth-aachen.de Wed Jun 28 17:47:08 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!rwth-aachen!asato From: asato@rwth-aachen.de (Andrei Sato) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jun28.174708.3162@rwth-aachen.de> Date: Wed, 28 Jun 1995 17:47:08 GMT References: <1995Jun25.035808.2779@purdue.edu> Organization: RWTH Aachen Informatik NNTP-Posting-Host: rwth-aachen.de X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Jun25.035808.2779@purdue.edu>, nhernandez@purdue.edu (Nadine Hernández) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire). -- Andrei Sato Tape trading list upon request. SASE required for international mail. From okang@clari.net Thu Jun 29 07:34:08 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!clari!okang From: okang@clari.net (Olga Kang) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jun29.073408.8960@clari.net> Date: Thu, 29 Jun 1995 07:34:08 GMT References: <1995Jun25.035808.2779@purdue.edu> Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1995Jun25.035808.2779@purdue.edu>, nhernandez@purdue.edu (Nadine Hernández) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- === Olga Kang === Dept of Electrical Engineering, ClariNet Communications Corp "5 sigma is a discovery. 7 is a question."