From eeriksson@cern.ch Wed Jun 21 11:58:48 1995
Path: ashpoly!cascade!mxgate!coyoacan!cern!eeriksson
From: eeriksson@cern.ch (Élodie Eriksson)
Newsgroups: comp.sys.m68k
Subject: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jun21.115848.9082@cern.ch>
Date: Wed, 21 Jun 1995 11:58:48 GMT
Organization: European Laboratory for Particle Physics, Geneva
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket?

-- 
Élodie Eriksson
Tape trading list upon request. SASE required for international mail.

From mrobertson@clari.net Fri Jun 23 12:29:48 1995
Path: ashpoly!cascade!transat!ukc!fennimore!clari!mrobertson
From: mrobertson@clari.net (Marisol Robertson)
Newsgroups: comp.sys.m68k
Subject: Re: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jun23.122948.9346@clari.net>
Date: Fri, 23 Jun 1995 12:29:48 GMT
References: <1995Jun21.115848.9082@cern.ch>
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In article <1995Jun21.115848.9082@cern.ch>, eeriksson@cern.ch (Élodie Eriksson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP?

-- 
Marisol Robertson | mrobertson@clari.net
PGP Key fingerprint: DD83 27F3 1DC3 F5FB
"Keep the channels open."

From mlindqvist@mit.edu Sun Jun 25 02:20:48 1995
Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!mlindqvist
From: mlindqvist@mit.edu (Matthias Lindqvist)
Newsgroups: comp.sys.m68k
Subject: Re: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jun25.022048.4174@mit.edu>
Date: Sun, 25 Jun 1995 02:20:48 GMT
References: <1995Jun21.115848.9082@cern.ch>
Organization: Massachusetts Institute of Technology
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In article <1995Jun21.115848.9082@cern.ch>, eeriksson@cern.ch (Élodie Eriksson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon.

-- 
Matthias Lindqvist
Opinions expressed are solely my own and not those of Massachusetts Institute of Technology.
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