From msmirnov@cern.ch Sat Oct 28 20:49:36 1995
Path: ashpoly!bigsur!pacrim!krgate!eunha!cern!msmirnov
From: msmirnov@cern.ch (Mikhail Smirnov)
Newsgroups: comp.sys.m68k
Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct28.204936.3147@cern.ch>
Date: Sat, 28 Oct 1995 20:49:36 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
Mikhail Smirnov -- European Laboratory for Particle Physics, Geneva
"There are 14 nodes and only 10 countries. Count again."

From mkuznetsov@stanford.edu Sun Oct 29 22:00:36 1995
Path: ashpoly!bigsur!pacrim!jpgate!kamome!stanford!mkuznetsov
From: mkuznetsov@stanford.edu (Marta Kuznetsov)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct29.220036.4061@stanford.edu>
Date: Sun, 29 Oct 1995 22:00:36 GMT
References: <1995Oct28.204936.3147@cern.ch>
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In article <1995Oct28.204936.3147@cern.ch>, msmirnov@cern.ch (Mikhail Smirnov) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
Marta Kuznetsov
Tape trading list upon request. SASE required for international mail.