From esilva@netcom.com Mon Jan 01 17:18:25 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!netcom!esilva From: esilva@netcom.com (Elaine Silva) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan01.171825.1000@netcom.com> Date: Mon, 01 Jan 1996 17:18:25 GMT Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: WinVN 0.99.5 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Elaine Silva Opinions expressed are solely my own and not those of NETCOM On-Line Communication Services. ------------------------------------------------------------ From jcampbell@kth.se Tue Jan 02 15:01:25 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!kth!jcampbell From: jcampbell@kth.se (Julien Campbell) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan02.150125.1125@kth.se> Date: Tue, 02 Jan 1996 15:01:25 GMT References: <1996Jan01.171825.1000@netcom.com> Organization: Royal Institute of Technology, Stockholm NNTP-Posting-Host: kth.se X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1996Jan01.171825.1000@netcom.com>, esilva@netcom.com (Elaine Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs. -- Julien Campbell US Robotics Courier V.34 @ 19,200 bps "The hatch is open. Is anyone listening?" From toliveira@panix.com Thu Jan 04 02:45:25 1996 Path: ashpoly!cascade!mxgate!coyoacan!panix!toliveira From: toliveira@panix.com (Thiago Oliveira) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan04.024525.7257@panix.com> Date: Thu, 04 Jan 1996 02:45:25 GMT References: <1996Jan01.171825.1000@netcom.com> <1996Jan02.150125.1125@kth.se> Organization: Public Access Unix of New York NNTP-Posting-Host: panix.com X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1996Jan02.150125.1125@kth.se>, jcampbell@kth.se (Julien Campbell) writes: > Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs. -- Thiago Oliveira -- Public Access Unix of New York "When every node is whole, the channel opens." From lstewart@utexas.edu Fri Jan 05 11:19:25 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!utexas!lstewart From: lstewart@utexas.edu (Liam Stewart) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan05.111925.4507@utexas.edu> Date: Fri, 05 Jan 1996 11:19:25 GMT References: <1996Jan01.171825.1000@netcom.com> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Jan01.171825.1000@netcom.com>, esilva@netcom.com (Elaine Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Liam Stewart | lstewart@utexas.edu PGP Key fingerprint: A3E8 6222 D28D 7274 "Keep the channels open." From mandersson@pipeline.com Sun Jan 07 14:41:25 1996 Path: ashpoly!cascade!mxgate!coyoacan!pipeline!mandersson From: mandersson@pipeline.com (Mathieu Andersson) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan07.144125.1394@pipeline.com> Date: Sun, 07 Jan 1996 14:41:25 GMT References: <1996Jan01.171825.1000@netcom.com> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Jan01.171825.1000@netcom.com>, esilva@netcom.com (Elaine Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- === Mathieu Andersson === Dept of Electrical Engineering, The Pipeline Internet Network "The carrier frequency does not drift by accident."