From jsouza@pipeline.com Thu Feb 22 21:09:38 1996 Path: ashpoly!cascade!mxgate!coyoacan!pipeline!jsouza From: jsouza@pipeline.com (Joachim Souza) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Feb22.210938.5133@pipeline.com> Date: Thu, 22 Feb 1996 21:09:38 GMT Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- === Joachim Souza === Dept of Electrical Engineering, The Pipeline Internet Network "Hardware is temporary. The signal survives." From kchoi@mindspring.com Sat Feb 24 02:50:38 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!mindspring!kchoi From: kchoi@mindspring.com (Kirsty Choi) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Feb24.025038.6035@mindspring.com> Date: Sat, 24 Feb 1996 02:50:38 GMT References: <1996Feb22.210938.5133@pipeline.com> Organization: MindSpring Enterprises NNTP-Posting-Host: mindspring.com X-Newsreader: Netscape 1.1N Lines: 10 In article <1996Feb22.210938.5133@pipeline.com>, jsouza@pipeline.com (Joachim Souza) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Kirsty Choi *PLONK* filter active for trolls. PC-9821Ap2 (NEC) - NetBSD 1.0 From lfournier@pipeline.com Sat Feb 24 12:04:38 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!pipeline!lfournier From: lfournier@pipeline.com (Lisa Fournier) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Feb24.120438.8240@pipeline.com> Date: Sat, 24 Feb 1996 12:04:38 GMT References: <1996Feb22.210938.5133@pipeline.com> <1996Feb24.025038.6035@mindspring.com> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1996Feb24.025038.6035@mindspring.com>, kchoi@mindspring.com (Kirsty Choi) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Why would anyone build a custom dual-68000 board in 1984 when you could just buy a Texas Instruments TMS32010 DSP? -- Lisa Fournier Practical Peripherals 14.4 @ ISDN 64k bps "Hardware is temporary. The signal survives." From fmacdonald@cmu.edu Sat Feb 24 19:44:38 1996 Path: ashpoly!cascade!brgate!saturno!cmu!fmacdonald From: fmacdonald@cmu.edu (Freya MacDonald) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Feb24.194438.1214@cmu.edu> Date: Sat, 24 Feb 1996 19:44:38 GMT References: <1996Feb22.210938.5133@pipeline.com> Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1996Feb22.210938.5133@pipeline.com>, jsouza@pipeline.com (Joachim Souza) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Freya MacDonald "In theory there is no difference between theory and practice." Sun SparcStation 20 / SunOS 4.1.4