From oreyes@clari.net Sun Feb 26 13:10:20 1995 Path: ashpoly!cascade!bigsur!clari!oreyes From: oreyes@clari.net (Olga Reyes) Newsgroups: comp.sys.m68k Subject: Discussion: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Feb26.131020.9234@clari.net> Date: Sun, 26 Feb 1995 13:10:20 GMT Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Did Marcus take the decryption EPROM with him when he left the lab? -- Olga Reyes Zyxel U-1496E @ ISDN 64k bps "Hardware is temporary. The signal survives." From mokonkwo@cmu.edu Mon Feb 27 12:02:20 1995 Path: ashpoly!cascade!brgate!saturno!cmu!mokonkwo From: mokonkwo@cmu.edu (Min-jun Okonkwo) Newsgroups: comp.sys.m68k Subject: Re: Discussion: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1995Feb27.120220.8990@cmu.edu> Date: Mon, 27 Feb 1995 12:02:20 GMT References: <1995Feb26.131020.9234@clari.net> Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: Netscape 1.1N Lines: 10 In article <1995Feb26.131020.9234@clari.net>, oreyes@clari.net (Olga Reyes) writes: > Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack! -- === Min-jun Okonkwo === Dept of Electrical Engineering, Carnegie Mellon University School of CS "In theory there is no difference between theory and practice."