From ogirard@mit.edu Thu Aug 11 09:25:36 1994 Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!ogirard From: ogirard@mit.edu (Olga Girard) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Aug11.092536.9661@mit.edu> Date: Thu, 11 Aug 1994 09:25:36 GMT Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Olga Girard "When every node is whole, the channel opens." Atari Falcon 030 / AmigaOS 3.1 From seriksson@earthlink.net Fri Aug 12 05:28:36 1994 Path: ashpoly!cascade!transat!eunet-fr!teletel!earthlink!seriksson From: seriksson@earthlink.net (Sergei Eriksson) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Aug12.052836.8891@earthlink.net> Date: Fri, 12 Aug 1994 05:28:36 GMT References: <1994Aug11.092536.9661@mit.edu> Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1994Aug11.092536.9661@mit.edu>, ogirard@mit.edu (Olga Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Top-posters will be placed in my ~/.killfile without notice. -- Sergei Eriksson *PLONK* filter active for trolls. Macintosh IIfx - NetBSD 1.0 From ymoreau@cam.ac.uk Fri Aug 12 13:27:36 1994 Path: ashpoly!cascade!brgate!saturno!cam!ymoreau From: ymoreau@cam.ac.uk (Yuki Moreau) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Aug12.132736.4515@cam.ac.uk> Date: Fri, 12 Aug 1994 13:27:36 GMT References: <1994Aug11.092536.9661@mit.edu> Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1994Aug11.092536.9661@mit.edu>, ogirard@mit.edu (Olga Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Yuki Moreau "Row 14. No joke." Atari Falcon 030 / Linux 1.2.13 From sgirard@purdue.edu Sat Aug 13 06:03:36 1994 Path: ashpoly!cascade!bigsur!purdue!sgirard From: sgirard@purdue.edu (Seo-yeon Girard) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Aug13.060336.5041@purdue.edu> Date: Sat, 13 Aug 1994 06:03:36 GMT References: <1994Aug11.092536.9661@mit.edu> <1994Aug12.052836.8891@earthlink.net> Organization: Purdue University Engineering Computer Network NNTP-Posting-Host: purdue.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1994Aug12.052836.8891@earthlink.net>, seriksson@earthlink.net (Sergei Eriksson) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Unsubscribe me from this list! (Wait, this is Usenet, never mind). -- Seo-yeon Girard *PLONK* filter active for trolls. PC-9821Ap2 (NEC) - NetBSD 1.0