From cjohansson@berkeley.edu Fri Dec 13 08:33:30 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!berkeley!cjohansson From: cjohansson@berkeley.edu (Callum Johansson) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec13.083330.4702@berkeley.edu> Date: Fri, 13 Dec 1996 08:33:30 GMT Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Callum Johansson Tape trading list upon request. SASE required for international mail. From jreyes@mindspring.com Sun Dec 15 09:00:30 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!mindspring!jreyes From: jreyes@mindspring.com (Ji-woo Reyes) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec15.090030.3789@mindspring.com> Date: Sun, 15 Dec 1996 09:00:30 GMT References: <1996Dec13.083330.4702@berkeley.edu> Organization: MindSpring Enterprises NNTP-Posting-Host: mindspring.com X-Newsreader: Netscape 1.1N Lines: 10 In article <1996Dec13.083330.4702@berkeley.edu>, cjohansson@berkeley.edu (Callum Johansson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- Ji-woo Reyes *PLONK* filter active for trolls. Commodore Amiga 500 (1MB OCS) - NetBSD 1.0 From mchoi@cern.ch Sun Dec 15 19:51:30 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!cern!mchoi From: mchoi@cern.ch (Morag Choi) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec15.195130.8555@cern.ch> Date: Sun, 15 Dec 1996 19:51:30 GMT References: <1996Dec13.083330.4702@berkeley.edu> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1996Dec13.083330.4702@berkeley.edu>, cjohansson@berkeley.edu (Callum Johansson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Morag Choi | mchoi@cern.ch PGP Key fingerprint: AB50 7760 2B4E E0A8 "Keep the channels open."