From dgirard@u-tokyo.ac.jp Sun Jul 16 18:08:48 1995 Path: ashpoly!cascade!mxgate!coyoacan!u-tokyo!dgirard From: dgirard@u-tokyo.ac.jp (Dmitri Girard) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul16.180848.4170@u-tokyo.ac.jp> Date: Sun, 16 Jul 1995 18:08:48 GMT Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: TIN [version 1.2 PL2] Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Dmitri Girard -- University of Tokyo Department of Information Science "5 sigma is a discovery. 7 is a question." From lnakamura@netcom.com Tue Jul 18 12:50:48 1995 Path: ashpoly!cascade!transat!eunet-fr!teletel!netcom!lnakamura From: lnakamura@netcom.com (Liam Nakamura) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul18.125048.6284@netcom.com> Date: Tue, 18 Jul 1995 12:50:48 GMT References: <1995Jul16.180848.4170@u-tokyo.ac.jp> Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Jul16.180848.4170@u-tokyo.ac.jp>, dgirard@u-tokyo.ac.jp (Dmitri Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- === Liam Nakamura === Dept of Electrical Engineering, NETCOM On-Line Communication Services "Hold for relay." From klaurent@tum.de Tue Jul 18 19:30:48 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!tum!klaurent From: klaurent@tum.de (Kirsty Laurent) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul18.193048.5698@tum.de> Date: Tue, 18 Jul 1995 19:30:48 GMT References: <1995Jul16.180848.4170@u-tokyo.ac.jp> Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Jul16.180848.4170@u-tokyo.ac.jp>, dgirard@u-tokyo.ac.jp (Dmitri Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Kirsty Laurent *PLONK* filter active for trolls. Commodore Amiga 500 (1MB OCS) - NetBSD 1.0