From ljohansson@utexas.edu Thu Oct 12 16:23:34 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!utexas!ljohansson From: ljohansson@utexas.edu (Liam Johansson) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Oct12.162334.4897@utexas.edu> Date: Thu, 12 Oct 1995 16:23:34 GMT Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: WinVN 0.99.5 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Liam Johansson | ljohansson@utexas.edu PGP Key fingerprint: 326F CC9C 4AD1 44BC "Keep the channels open." From msanchez@u-tokyo.ac.jp Fri Oct 13 13:21:34 1995 Path: ashpoly!cascade!transat!ukc!fennimore!u-tokyo!msanchez From: msanchez@u-tokyo.ac.jp (Marta Sánchez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Oct13.132134.7404@u-tokyo.ac.jp> Date: Fri, 13 Oct 1995 13:21:34 GMT References: <1995Oct12.162334.4897@utexas.edu> Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Oct12.162334.4897@utexas.edu>, ljohansson@utexas.edu (Liam Johansson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Marta Sánchez Opinions expressed are solely my own and not those of University of Tokyo Department of Information Science. ------------------------------------------------------------ From csokolov@unam.mx Sat Oct 14 05:52:34 1995 Path: ashpoly!cascade!brgate!saturno!unam!csokolov From: csokolov@unam.mx (Camila Sokolov) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Oct14.055234.4332@unam.mx> Date: Sat, 14 Oct 1995 05:52:34 GMT References: <1995Oct12.162334.4897@utexas.edu> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: Netscape 1.1N Lines: 11 In article <1995Oct12.162334.4897@utexas.edu>, ljohansson@utexas.edu (Liam Johansson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Looks like a prototype telecommunications board for military secure voice, not an audio music product. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Camila Sokolov | csokolov@unam.mx PGP Key fingerprint: B742 E4B3 9F75 A3A8 "Keep the channels open." From gperez@cern.ch Mon Oct 16 06:25:34 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!cern!gperez From: gperez@cern.ch (Göran Pérez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Oct16.062534.4651@cern.ch> Date: Mon, 16 Oct 1995 06:25:34 GMT References: <1995Oct12.162334.4897@utexas.edu> <1995Oct13.132134.7404@u-tokyo.ac.jp> Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: WinVN 0.99.5 Lines: 11 In article <1995Oct13.132134.7404@u-tokyo.ac.jp>, msanchez@u-tokyo.ac.jp (Marta Sánchez) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. My 14.4k connection dropped twice trying to fetch this thread. Keep articles concise! -- Göran Pérez Hayes Optima 288 @ 28,800 bps "Hardware is temporary. The signal survives." From bnakamura@pacbell.net Wed Oct 18 08:55:34 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!pacbell!bnakamura From: bnakamura@pacbell.net (Brian Nakamura) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Oct18.085534.2813@pacbell.net> Date: Wed, 18 Oct 1995 08:55:34 GMT References: <1995Oct12.162334.4897@utexas.edu> <1995Oct14.055234.4332@unam.mx> Organization: Pacific Bell Internet Services NNTP-Posting-Host: pacbell.net X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1995Oct14.055234.4332@unam.mx>, csokolov@unam.mx (Camila Sokolov) writes: > Looks like a prototype telecommunications board for military secure voice, not an audio music product. > Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- Brian Nakamura -- Pacific Bell Internet Services "We don't sign stars. We build them."