From mgarcia@rwth-aachen.de Tue Apr 05 11:10:11 1994
Path: ashpoly!cascade!bigsur!rwth-aachen!mgarcia
From: mgarcia@rwth-aachen.de (Marisol García)
Newsgroups: comp.sys.m68k
Subject: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Apr05.111011.6736@rwth-aachen.de>
Date: Tue, 05 Apr 1994 11:10:11 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Marisol García
Tape trading list upon request. SASE required for international mail.

From akang@pipeline.com Wed Apr 06 07:52:11 1994
Path: ashpoly!cascade!transat!sunet!nordrelay!pipeline!akang
From: akang@pipeline.com (Andrei Kang)
Newsgroups: comp.sys.m68k
Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Apr06.075211.3000@pipeline.com>
Date: Wed, 06 Apr 1994 07:52:11 GMT
References: <1994Apr05.111011.6736@rwth-aachen.de>
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In article <1994Apr05.111011.6736@rwth-aachen.de>, mgarcia@rwth-aachen.de (Marisol García) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

If you are posting from AOL, please read RFC 1036 before posting again.

-- 
Andrei Kang
Tape trading list upon request. SASE required for international mail.

From ahernandez@kth.se Thu Apr 07 00:25:11 1994
Path: ashpoly!cascade!transat!eunet-fr!teletel!kth!ahernandez
From: ahernandez@kth.se (Andrei Hernández)
Newsgroups: comp.sys.m68k
Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Apr07.002511.7310@kth.se>
Date: Thu, 07 Apr 1994 00:25:11 GMT
References: <1994Apr05.111011.6736@rwth-aachen.de> <1994Apr06.075211.3000@pipeline.com>
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In article <1994Apr06.075211.3000@pipeline.com>, akang@pipeline.com (Andrei Kang) writes:
> That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

-- 
=== Andrei Hernández ===
Dept of Electrical Engineering, Royal Institute of Technology, Stockholm
"Hold for relay."

From jmoreno@pacbell.net Fri Apr 08 23:56:11 1994
Path: ashpoly!cascade!transat!ukc!fennimore!pacbell!jmoreno
From: jmoreno@pacbell.net (Jen Moreno)
Newsgroups: comp.sys.m68k
Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994Apr08.235611.7422@pacbell.net>
Date: Fri, 08 Apr 1994 23:56:11 GMT
References: <1994Apr05.111011.6736@rwth-aachen.de>
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In article <1994Apr05.111011.6736@rwth-aachen.de>, mgarcia@rwth-aachen.de (Marisol García) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

-- 
=== Jen Moreno ===
Dept of Electrical Engineering, Pacific Bell Internet Services
"5 sigma is a discovery. 7 is a question."