From dkowalski@tum.de Thu Sep 28 02:48:58 1995 Path: ashpoly!cascade!brgate!saturno!tum!dkowalski From: dkowalski@tum.de (Diego Kowalski) Newsgroups: comp.sys.m68k Subject: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep28.024858.8732@tum.de> Date: Thu, 28 Sep 1995 02:48:58 GMT Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Diego Kowalski Practical Peripherals 14.4 @ 33,600 bps "They will send a copy in my place." From mmuller@berkeley.edu Sat Sep 30 00:17:58 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!berkeley!mmuller From: mmuller@berkeley.edu (Mei Müller) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep30.001758.8189@berkeley.edu> Date: Sat, 30 Sep 1995 00:17:58 GMT References: <1995Sep28.024858.8732@tum.de> Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1995Sep28.024858.8732@tum.de>, dkowalski@tum.de (Diego Kowalski) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Mei Müller Tape trading list upon request. SASE required for international mail.