From jstewart@illinois.edu Sun Sep 17 09:16:03 1995 Path: ashpoly!cascade!brgate!saturno!illinois!jstewart From: jstewart@illinois.edu (Julien Stewart) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep17.091603.6145@illinois.edu> Date: Sun, 17 Sep 1995 09:16:03 GMT Organization: University of Illinois Urbana-Champaign NNTP-Posting-Host: illinois.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Julien Stewart Zyxel U-1496E @ 33,600 bps "There are 14 nodes and only 10 countries. Count again." From mhernandez@hanse.de Mon Sep 18 20:27:03 1995 Path: ashpoly!cascade!bigsur!hanse!mhernandez From: mhernandez@hanse.de (Morag Hernández) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Sep18.202703.5762@hanse.de> Date: Mon, 18 Sep 1995 20:27:03 GMT References: <1995Sep17.091603.6145@illinois.edu> Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1995Sep17.091603.6145@illinois.edu>, jstewart@illinois.edu (Julien Stewart) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire). -- Morag Hernández "Row 14. No joke." Sun SparcStation 20 / Linux 1.2.13