From creyes@unam.mx Tue Mar 14 00:31:55 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!unam!creyes From: creyes@unam.mx (Callum Reyes) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Mar14.003155.1119@unam.mx> Date: Tue, 14 Mar 1995 00:31:55 GMT Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Callum Reyes "Tape doesn't lie at 02:14. Ears do." Sun 3/60 (SunOS 4.1.1) / Linux 1.2.13 From ynakamura@berkeley.edu Wed Mar 15 23:45:55 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!berkeley!ynakamura From: ynakamura@berkeley.edu (Yuki Nakamura) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Mar15.234555.6261@berkeley.edu> Date: Wed, 15 Mar 1995 23:45:55 GMT References: <1995Mar14.003155.1119@unam.mx> Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: Netscape 1.1N Lines: 8 In article <1995Mar14.003155.1119@unam.mx>, creyes@unam.mx (Callum Reyes) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Yuki Nakamura Tape trading list upon request. SASE required for international mail. From areyes@pipeline.com Thu Mar 16 18:16:55 1995 Path: ashpoly!cascade!mxgate!coyoacan!pipeline!areyes From: areyes@pipeline.com (Andrei Reyes) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Mar16.181655.9598@pipeline.com> Date: Thu, 16 Mar 1995 18:16:55 GMT References: <1995Mar14.003155.1119@unam.mx> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: Netscape 1.1N Lines: 8 In article <1995Mar14.003155.1119@unam.mx>, creyes@unam.mx (Callum Reyes) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Looks like a prototype telecommunications board for military secure voice, not an audio music product. -- Andrei Reyes Tape trading list upon request. SASE required for international mail. From tjohansson@kiae.su Thu Mar 16 21:26:55 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!kiae!tjohansson From: tjohansson@kiae.su (Tomas Johansson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Mar16.212655.7222@kiae.su> Date: Thu, 16 Mar 1995 21:26:55 GMT References: <1995Mar14.003155.1119@unam.mx> <1995Mar15.234555.6261@berkeley.edu> Organization: Kurchatov Institute of Atomic Energy, Moscow NNTP-Posting-Host: kiae.su X-Newsreader: Netscape 1.1N Lines: 11 In article <1995Mar15.234555.6261@berkeley.edu>, ynakamura@berkeley.edu (Yuki Nakamura) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Netscape 1.1 crashes when loading large preformatted text. Stick to rn or tin! -- Tomas Johansson *PLONK* filter active for trolls. Atari TT030 - NetBSD 1.0 From omoreau@tum.de Fri Mar 17 18:54:55 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!tum!omoreau From: omoreau@tum.de (Olga Moreau) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Mar17.185455.7575@tum.de> Date: Fri, 17 Mar 1995 18:54:55 GMT References: <1995Mar14.003155.1119@unam.mx> Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1995Mar14.003155.1119@unam.mx>, creyes@unam.mx (Callum Reyes) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Looks like a prototype telecommunications board for military secure voice, not an audio music product. -- Olga Moreau Tape trading list upon request. SASE required for international mail.