From estewart@utexas.edu Fri Feb 10 04:29:02 1995 Path: ashpoly!cascade!transat!sunet!nordrelay!utexas!estewart From: estewart@utexas.edu (Elaine Stewart) Newsgroups: comp.sys.m68k Subject: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Feb10.042902.9412@utexas.edu> Date: Fri, 10 Feb 1995 04:29:02 GMT Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: WinVN 0.99.5 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Elaine Stewart US Robotics Courier V.34 @ 19,200 bps "5 sigma is a discovery. 7 is a question." From mgirard@netcom.com Fri Feb 10 18:50:02 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!netcom!mgirard From: mgirard@netcom.com (Marisol Girard) Newsgroups: comp.sys.m68k Subject: Re: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Feb10.185002.2607@netcom.com> Date: Fri, 10 Feb 1995 18:50:02 GMT References: <1995Feb10.042902.9412@utexas.edu> Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: Netscape 1.1N Lines: 8 In article <1995Feb10.042902.9412@utexas.edu>, estewart@utexas.edu (Elaine Stewart) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Marisol Girard Tape trading list upon request. SASE required for international mail. From ssouza@stanford.edu Sun Feb 12 20:29:02 1995 Path: ashpoly!cascade!bigsur!stanford!ssouza From: ssouza@stanford.edu (Steve Souza) Newsgroups: comp.sys.m68k Subject: Re: [FLAME] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Feb12.202902.7747@stanford.edu> Date: Sun, 12 Feb 1995 20:29:02 GMT References: <1995Feb10.042902.9412@utexas.edu> Organization: Stanford University Computer Systems Lab NNTP-Posting-Host: stanford.edu X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1995Feb10.042902.9412@utexas.edu>, estewart@utexas.edu (Elaine Stewart) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Looks like a prototype telecommunications board for military secure voice, not an audio music product. Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns. -- Steve Souza | ssouza@stanford.edu PGP Key fingerprint: 9F7F 5D9A A457 00A5 "Keep the channels open."