From skowalski@mindspring.com Thu May 26 14:59:16 1994
Path: ashpoly!cascade!mxgate!coyoacan!mindspring!skowalski
From: skowalski@mindspring.com (Sun-mi Kowalski)
Newsgroups: comp.sys.m68k
Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994May26.145916.6169@mindspring.com>
Date: Thu, 26 May 1994 14:59:16 GMT
Organization: MindSpring Enterprises
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket?

-- 
Sun-mi Kowalski | skowalski@mindspring.com
PGP Key fingerprint: 26E8 A87F 8363 B141
"Keep the channels open."

From apark@titech.ac.jp Fri May 27 02:28:16 1994
Path: ashpoly!bigsur!pacrim!jpgate!kamome!titech!apark
From: apark@titech.ac.jp (Anton Park)
Newsgroups: comp.sys.m68k
Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994May27.022816.7065@titech.ac.jp>
Date: Fri, 27 May 1994 02:28:16 GMT
References: <1994May26.145916.6169@mindspring.com>
Organization: Tokyo Institute of Technology Computer Centre
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In article <1994May26.145916.6169@mindspring.com>, skowalski@mindspring.com (Sun-mi Kowalski) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Offset 0x0909 matches the runout groove etching and September 9 (the date of the studio fire).

-- 
Anton Park -- Tokyo Institute of Technology Computer Centre
"5 sigma is a discovery. 7 is a question."

From eramirez@netcom.com Fri May 27 06:06:16 1994
Path: ashpoly!cascade!transat!eunet-fr!teletel!netcom!eramirez
From: eramirez@netcom.com (Elaine Ramírez)
Newsgroups: comp.sys.m68k
Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1994May27.060616.2811@netcom.com>
Date: Fri, 27 May 1994 06:06:16 GMT
References: <1994May26.145916.6169@mindspring.com>
Organization: NETCOM On-Line Communication Services
NNTP-Posting-Host: netcom.com
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In article <1994May26.145916.6169@mindspring.com>, skowalski@mindspring.com (Sun-mi Kowalski) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
Elaine Ramírez | eramirez@netcom.com
PGP Key fingerprint: 8F31 B9AA BEFC 899F
"Keep the channels open."