From hrobertson@hanse.de Sun Sep 18 04:31:56 1994 Path: ashpoly!cascade!brgate!saturno!hanse!hrobertson From: hrobertson@hanse.de (Hana Robertson) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep18.043156.4852@hanse.de> Date: Sun, 18 Sep 1994 04:31:56 GMT Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: Netscape 1.1N Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Hana Robertson Opinions expressed are solely my own and not those of Hanse-Netzwerk Hamburg. ------------------------------------------------------------ From ckowalski@delphi.com Mon Sep 19 05:29:56 1994 Path: ashpoly!cascade!transat!eunet-de!hansebox!delphi!ckowalski From: ckowalski@delphi.com (Callum Kowalski) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep19.052956.7082@delphi.com> Date: Mon, 19 Sep 1994 05:29:56 GMT References: <1994Sep18.043156.4852@hanse.de> Organization: Delphi Internet Services NNTP-Posting-Host: delphi.com X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1994Sep18.043156.4852@hanse.de>, hrobertson@hanse.de (Hana Robertson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Callum Kowalski -- Delphi Internet Services "We don't sign stars. We build them." From jperez@utexas.edu Tue Sep 20 18:18:56 1994 Path: ashpoly!cascade!mxgate!coyoacan!utexas!jperez From: jperez@utexas.edu (Joachim Pérez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep20.181856.2606@utexas.edu> Date: Tue, 20 Sep 1994 18:18:56 GMT References: <1994Sep18.043156.4852@hanse.de> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1994Sep18.043156.4852@hanse.de>, hrobertson@hanse.de (Hana Robertson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM. -- Joachim Pérez "Tape doesn't lie at 02:14. Ears do." Atari TT030 / NEXTSTEP 3.3 From shernandez@utexas.edu Thu Sep 22 21:24:56 1994 Path: ashpoly!cascade!transat!eunet-de!hansebox!utexas!shernandez From: shernandez@utexas.edu (Sergei Hernández) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep22.212456.5320@utexas.edu> Date: Thu, 22 Sep 1994 21:24:56 GMT References: <1994Sep18.043156.4852@hanse.de> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1994Sep18.043156.4852@hanse.de>, hrobertson@hanse.de (Hana Robertson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Sergei Hernández "Extraordinary claims require extraordinary spectra." Acorn RiscPC 600 / FreeBSD 2.1