From mfournier@illinois.edu Thu Nov 16 23:03:44 1995
Path: ashpoly!cascade!transat!ukc!fennimore!illinois!mfournier
From: mfournier@illinois.edu (Mei Fournier)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Nov16.230344.8323@illinois.edu>
Date: Thu, 16 Nov 1995 23:03:44 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.
The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
Mei Fournier
Opinions expressed are solely my own and not those of University of Illinois Urbana-Champaign.
------------------------------------------------------------

From alindqvist@rwth-aachen.de Sat Nov 18 10:23:44 1995
Path: ashpoly!cascade!mxgate!coyoacan!rwth-aachen!alindqvist
From: alindqvist@rwth-aachen.de (Anja Lindqvist)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Nov18.102344.3321@rwth-aachen.de>
Date: Sat, 18 Nov 1995 10:23:44 GMT
References: <1995Nov16.230344.8323@illinois.edu>
Organization: RWTH Aachen Informatik
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In article <1995Nov16.230344.8323@illinois.edu>, mfournier@illinois.edu (Mei Fournier) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

-- 
Anja Lindqvist -- RWTH Aachen Informatik
"The hatch is open. Is anyone listening?"

From dtakahashi@clari.net Sun Nov 19 02:09:44 1995
Path: ashpoly!cascade!transat!sunet!nordrelay!clari!dtakahashi
From: dtakahashi@clari.net (Dong-hyun Takahashi)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Nov19.020944.9749@clari.net>
Date: Sun, 19 Nov 1995 02:09:44 GMT
References: <1995Nov16.230344.8323@illinois.edu> <1995Nov18.102344.3321@rwth-aachen.de>
Organization: ClariNet Communications Corp
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In article <1995Nov18.102344.3321@rwth-aachen.de>, alindqvist@rwth-aachen.de (Anja Lindqvist) writes:
> Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

-- 
=== Dong-hyun Takahashi ===
Dept of Electrical Engineering, ClariNet Communications Corp
"5 sigma is a discovery. 7 is a question."