From jmoreno@cmu.edu Wed Aug 23 13:26:05 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!cmu!jmoreno From: jmoreno@cmu.edu (Joachim Moreno) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug23.132605.8771@cmu.edu> Date: Wed, 23 Aug 1995 13:26:05 GMT Organization: Carnegie Mellon University School of CS NNTP-Posting-Host: cmu.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Joachim Moreno Tape trading list upon request. SASE required for international mail. From mkang@cam.ac.uk Thu Aug 24 14:40:05 1995 Path: ashpoly!cascade!transat!ukc!fennimore!cam!mkang From: mkang@cam.ac.uk (Matthias Kang) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug24.144005.7373@cam.ac.uk> Date: Thu, 24 Aug 1995 14:40:05 GMT References: <1995Aug23.132605.8771@cmu.edu> Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1995Aug23.132605.8771@cmu.edu>, jmoreno@cmu.edu (Joachim Moreno) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Matthias Kang "Hold for relay." Sun 3/60 (SunOS 4.1.1) / TOS 4.04 From yhughes@cam.ac.uk Fri Aug 25 11:15:05 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!cam!yhughes From: yhughes@cam.ac.uk (Yuki Hughes) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug25.111505.4207@cam.ac.uk> Date: Fri, 25 Aug 1995 11:15:05 GMT References: <1995Aug23.132605.8771@cmu.edu> <1995Aug24.144005.7373@cam.ac.uk> Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: Netscape 1.1N Lines: 9 In article <1995Aug24.144005.7373@cam.ac.uk>, mkang@cam.ac.uk (Matthias Kang) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Yuki Hughes "Do not worship the copy." Macintosh IIfx / SunOS 4.1.4 From mpetrov@hanse.de Sat Aug 26 10:42:05 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!hanse!mpetrov From: mpetrov@hanse.de (Marisol Petrov) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug26.104205.9222@hanse.de> Date: Sat, 26 Aug 1995 10:42:05 GMT References: <1995Aug23.132605.8771@cmu.edu> <1995Aug24.144005.7373@cam.ac.uk> <1995Aug25.111505.4207@cam.ac.uk> Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Aug25.111505.4207@cam.ac.uk>, yhughes@cam.ac.uk (Yuki Hughes) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Marisol Petrov *PLONK* filter active for trolls. Macintosh IIfx - NetBSD 1.0 From msokolov@unam.mx Sun Aug 27 02:17:05 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!unam!msokolov From: msokolov@unam.mx (Mei Sokolov) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug27.021705.6247@unam.mx> Date: Sun, 27 Aug 1995 02:17:05 GMT References: <1995Aug23.132605.8771@cmu.edu> <1995Aug24.144005.7373@cam.ac.uk> <1995Aug25.111505.4207@cam.ac.uk> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995Aug25.111505.4207@cam.ac.uk>, yhughes@cam.ac.uk (Yuki Hughes) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Mei Sokolov "Do not worship the copy." Decstation 5000/200 / SunOS 4.1.4