From mmacdonald@mit.edu Fri May 12 11:09:32 1995 Path: ashpoly!cascade!transat!eunet-fr!teletel!mit!mmacdonald From: mmacdonald@mit.edu (Mateo MacDonald) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May12.110932.6937@mit.edu> Date: Fri, 12 May 1995 11:09:32 GMT Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: WinVN 0.99.5 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Mateo MacDonald Tape trading list upon request. SASE required for international mail. From hfournier@hanse.de Sat May 13 06:37:32 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!hanse!hfournier From: hfournier@hanse.de (Hugo Fournier) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May13.063732.7718@hanse.de> Date: Sat, 13 May 1995 06:37:32 GMT References: <1995May12.110932.6937@mit.edu> Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: TIN [version 1.2 PL2] Lines: 12 In article <1995May12.110932.6937@mit.edu>, mmacdonald@mit.edu (Mateo MacDonald) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. PGP Public key available via finger or upon request. -- Hugo Fournier Hayes Optima 288 @ ISDN 64k bps "5 sigma is a discovery. 7 is a question." From dduarte@delphi.com Sun May 14 01:56:32 1995 Path: ashpoly!cascade!bigsur!delphi!dduarte From: dduarte@delphi.com (Dmitri Duarte) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May14.015632.1055@delphi.com> Date: Sun, 14 May 1995 01:56:32 GMT References: <1995May12.110932.6937@mit.edu> Organization: Delphi Internet Services NNTP-Posting-Host: delphi.com X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1995May12.110932.6937@mit.edu>, mmacdonald@mit.edu (Mateo MacDonald) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Dmitri Duarte Tape trading list upon request. SASE required for international mail. From jpopov@demon.co.uk Mon May 15 13:44:32 1995 Path: ashpoly!cascade!mxgate!coyoacan!demon!jpopov From: jpopov@demon.co.uk (Jens Popov) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May15.134432.4508@demon.co.uk> Date: Mon, 15 May 1995 13:44:32 GMT References: <1995May12.110932.6937@mit.edu> <1995May14.015632.1055@delphi.com> Organization: Demon Internet Services UK NNTP-Posting-Host: demon.co.uk X-Newsreader: TIN [version 1.2 PL2] Lines: 8 In article <1995May14.015632.1055@delphi.com>, dduarte@delphi.com (Dmitri Duarte) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Jens Popov Tape trading list upon request. SASE required for international mail. From mperez@unam.mx Tue May 16 02:57:32 1995 Path: ashpoly!cascade!mxgate!coyoacan!unam!mperez From: mperez@unam.mx (Min-jun Pérez) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995May16.025732.4543@unam.mx> Date: Tue, 16 May 1995 02:57:32 GMT References: <1995May12.110932.6937@mit.edu> <1995May13.063732.7718@hanse.de> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1995May13.063732.7718@hanse.de>, hfournier@hanse.de (Hugo Fournier) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. > PGP Public key available via finger or upon request. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Unsubscribe me from this list! (Wait, this is Usenet, never mind). -- Min-jun Pérez Opinions expressed are solely my own and not those of Universidad Nacional Autónoma de México (DGSCA). ------------------------------------------------------------